1. Field of the Invention
The present invention relates generally to integrated circuit package technology and, more particularly, to an increased capacity QFP semiconductor package which includes one or more internal power bars, exposed leads and an exposed die pad on the bottom surface of the package body thereof, and additional leads which protrude from side surfaces of the package body.
2. Description of the Related Art
Semiconductor dies are conventionally enclosed in plastic packages that provide protection from hostile environments and enable electrical interconnection between the semiconductor die and an underlying substrate such as a printed circuit board (PCB) or motherboard. The elements of such a package include a metal leadframe, an integrated circuit or semiconductor die, bonding material to attach the semiconductor die to the leadframe, bond wires which electrically connect pads on the semiconductor die to individual leads of the leadframe, and a hard plastic encapsulant material which covers the other components and forms the exterior of the semiconductor package commonly referred to as the package body.
The leadframe is the central supporting structure of such a package, and is typically fabricated by chemically etching or mechanically stamping a metal strip. A portion of the leadframe is internal to the package, i.e., completely surrounded by the plastic encapsulant or package body. Portions of the leads of the leadframe extend externally from the package body or are partially exposed therein for use in electrically connecting the package to another component. In certain semiconductor packages, a portion of the die pad of the leadframe also remains exposed within the package body.
Leadframes for semiconductor packages can be largely classified into copper-based leadframes (copper/iron/phosphorous; 99.8/0.01/0.025), copper alloy-based leadframes (copper/chromium/tin/zinc; 99.0/0.25/0.22), alloy 42-based leadframes (iron/nickel; 58.0/42.0), etc. according to the composition of the elements or materials included in the leadframe. Exemplary semiconductor packages or devices employing leadframes include a through-hole mounting dual type inline package (DIP), a surface mounting type quad flat package (QFP), and a small outline package (SOP).
As indicated above, one type of semiconductor package commonly including a leadframe is a quad flat pack (QFP) package. QFP semiconductor packages or devices are particularly advantageous for their smaller size and superior electrical performance. A typical QFP package comprises a thin, generally square package body defining four peripheral sides of substantially equal length. Protruding from each of the four peripheral sides of the package body are a plurality of leads which each have a generally gull-wing configuration. Portions of the leads are internal to the package body, and are electrically connected to respective ones of the pads or terminals of a semiconductor die also encapsulated within the package body. The semiconductor die is itself mounted to a die pad of the QFP package leadframe. In certain types of QFP packages referred to as QFP exposed pad packages, one surface of the die pad is exposed within the bottom surface of the package body.
In the electronics industry and, in particular, in high frequency applications such hard disk drives, digital television and other consumer electronics, there is an increasing need for QFP exposed pad packages of increased functional capacity, coupled with reduced size. One of the deficiencies of currently known QFP packages is attributable to the length at which the leads protrude from the sides of the package body, such protrusion length resulting in an increase in the overall size of the QFP package and further limiting the number of inputs/outputs (I/O's) which may be included therein. With recent trends toward high integration and high performance semiconductor dies, there is a need for QFP packages to have a larger number of I/O's with excellent thermal and electrical properties. In view of this need, conventional leadframe structures as currently known and integrated into existing QFP packages often prove to be unsatisfactory.
Another deficiency of existing QFP packages is the absence of power bars which are often needed for power supply or ground connection. In this regard, the semiconductor dies integrated into currently known QFP packages typically require a number of power leads and ground leads, in addition to signal leads. To reduce the number of signal leads, some of these prior art QFP packages are provided with internal power bars or ground rings which extend substantially perpendicularly relative to the signal leads. All the power supply wires are bonded and electrically connected to the power bar with all the ground wires being bonded and electrically connected to the ground rings so as to avoid the unnecessary use of the signal leads for power supply or ground. However, in currently known leadframe designs for QFP packages, the power bars and/or ground rings are often not connected to other support structures of the leadframe and thus “float,” thus necessitating that they be fixed to the remainder of the leadframe through the use of, for example, lead lock tape. As will be recognized, this use of lead lock tape renders the power bars and/or ground rings structurally unstable, with such instability often leading to poor flatness relative to the signal leads. Additionally, the inclusion of power bars in currently known leadframe configurations for QFP packages often carries a significant penalty attributable to the resultant increase in size of the leadframe, and hence the QFP package including the same.
In an attempt to address some of the deficiencies highlighted above in relation to QFP packages, there has been developed in the prior art ball grid array (BGA) and pin grid array (PGA) semiconductor packages or devices which employ the use of laminate, tape, or film circuit boards as opposed to leadframes. These particular types of semiconductor packages provide a relatively large number of I/O's, such I/O's being defined by solder balls or metal pins which are formed on a lower surface of the encapsulant or package body of the package, rather than on the side surfaces of the package body. However, the circuit boards integrated into these types of semiconductor packages are expensive and typically exhibit poor heat sink and electrical performance characteristics in comparison to semiconductor packages employing leadframes. In this regard, semiconductor packages or devices employing leadframes often exhibit good heat sink performance due to the semiconductor die being directly mounted on a metal (e.g., copper) die pad of the leadframe. Further, the die pad of the leadframe can be used as a ground area to improve the electrical properties of the semiconductor package. Such a structure is difficult to achieve in a semiconductor package employing a circuit board.
The present invention provides a QFP exposed pad package which addresses the aforementioned needs by providing increased I/O and one or more internal power bars, while still achieving a reduced overall size. The QFP package of the present invention includes exposed leads and an exposed die pad on the bottom surface of the package body thereof, and additional leads which protrude from side surfaces of the package body. The QFP package of the present invention is also provided through the use of standard, low-cost leadframe design techniques. These, as well as other features and attributes of the present invention will be discussed in more detail below.